Explore the San Gabriel Mountains with This Authoritative Hiking Guide

Escape the rapid-paced urban life of Southern California, and step into the open, rugged terrain of the San Gabriel Mountains. Here, amid forest, chaparral, and stream, you’ll revitalize yourself in nature’s unhurried environment. Visit Eaton Canyon Falls, the most popular waterfall in the Angeles National Forest. Enjoy a family-friendly hike to a historic fire lookout site on Vetter Mountain. Challenge yourself on the San Antonio Ridge, the hardest traverse in the Angeles.

Now in its 10th edition, Trail of the Angeles by David Harris and John W. Robinson has been the region’s trusted hiking guide for more than 45 years. It describes 100 spectacular trails—ranging from one-hour strolls to challenging two-day backcountry trips—in the mountain range that looms large over the Los Angeles Basin. Featuring 18 new hikes, Trail of the Angeles guides you into almost every corner of the San Gabriels.

Inside You’ll Find:

• Descriptions of 100 hikes, including 18 new outings



• Trip difficulty evaluations, season recommendations, length, and elevation gain/loss



• Historical photos and descriptions, including the first American Indian footpaths, early pioneer homesteads, and landmarks still visible from the Great Hiking Era



• “Trails That Used to Be”: ghost trails that have vanished or are now impassable



• BONUS: A folded full-color map detailing all the hikes described in the book

This second edition has been updated with new content on I/O systems in the context of general purpose processors found in a PC as well as microcontrollers found almost everywhere. The new edition provides practical examples of how to interface with peripherals using RS232, SPI, motor control, interrupts, wireless, and analog-to-digital conversion. High-level descriptions of I/O interfaces found in PCs include USB, SDRAM, WiFi, PCI Express, and others. In addition to expanded and updated material throughout, SystemVerilog is now featured in the programming and code examples (replacing Verilog), alongside VHDL. This new edition also provides additional exercises and a new appendix on C programming to strengthen the connection between programming and processor architecture.

• Covers the fundamentals of digital logic design and reinforces logic concepts through the design of a MIPS microprocessor.
• Features side-by-side examples of the two most prominent Hardware Description Languages (HDLs)—SystemVerilog and VHDL—which illustrate and compare the ways each can be used in the design of digital systems.
• Includes examples throughout the text that enhance the reader’s understanding and retention of key concepts and techniques.
• Companion Web site includes links to CAD tools for FPGA design from Altera and Mentor Graphics, lecture slides, laboratory projects, and solutions to exercises.

Updated based on instructor feedback with more exercises and new examples of parallel and advanced architectures, practical I/O applications, embedded systems, and heterogeneous computing

• Presents digital system design examples in both VHDL and SystemVerilog (updated for the second edition from Verilog), shown side-by-side to compare and contrast their strengths
• Includes a new chapter on C programming to provide necessary prerequisites and strengthen the connection between programming and processor architecture
• Companion Web site includes links to Xilinx CAD tools for FPGA design, lecture slides, laboratory projects, and solutions to exercises.

Instructors can also register at textbooks.elsevier.com for access to:

• Solutions to all exercises (PDF)
• Lab materials with solutions
• HDL for textbook examples and exercise solutions
• Lecture slides (PPT)
• Sample exams
• Sample course syllabus
• Figures from the text (JPG, PPT)

As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.

• Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial
• Provides incisive instruction and advice punctuated by humorous illustrations
• Includes exercises to test understanding of key concepts and solutions to selected exercises

Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.

The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.

• Explains the method and how to apply it in two practically focused chapters.
• Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
• Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
• Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.
• Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.
• Presents a complete derivation of the method-so you see how and why it works.